A structure of the kind shown in FIG. 6 has been proposed in the specification of Japanese Patent Kokai Publication No. JP-P2004-71646A (referred to as “Patent Document 1” below) as a non-volatile semiconductor storage device. In this non-volatile semiconductor storage device, as shown in FIG. 6, a channel is formed between an n+ diffusion region (also referred to as a heavily doped n+ region or n+ region) 107 and a buried diffusion region (layer) 121, and electric charge is captured in a storage node of an ONO film (stacked insulating films obtained by building up an oxide film, nitride film and oxide film in the order mentioned) on both sides of the cell, whereby it is possible to write, read and erase 2-bit information per cell independently. In FIG. 6, reference numeral 101 denotes a zone of memory cell diffusion region (p-well) (refereed to as a memory cell area), 103 a select gate and 111 a word line that intersects the select gate 103 and is disposed on the select gate 103 via an insulating film. Reference numeral 116 denotes a bit line of a first metallic interconnect layer (aluminum interconnect layer). Further, bank selection units 200A and 200B are located on both sides of the memory cell region. The select gates 103 extend alternatingly from one side of the memory cell area and from the opposite side of the memory cell area toward the opposing side.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2004-71646A